Many systems, including computer systems, must provide a generated clock signal that is synchronized to an input system clock signal that is generated externally. Phase lock loop ("PLL") technology is commonly used in this process. The system clock signal is input to a PLL, which generates the generated clock signal and then substantially locks its phase and frequency to a multiple of the system clock signal using feedback. FIG. 1A depicts a generic PLL circuit 10, comprising a phase detector 20, a loop filter 30, voltage controlled oscillator ("VCO") 40, and a digital divide-by-N unit 50.
A system clock signal is input to the non-inverting input of phase detector 20, and a clock signal output from the frequency divider 50 is input to the inverting input. The phase detector compares the phase of the two clock signals and generates an output error signal that is proportional to the phase difference, or offset. The error signal from the phase detector is then filtered by loop filter 30 to remove high frequency components. The filtered voltage from the output of the loop filter is then input to VCO 40, which outputs a frequency proportional to the voltage at the VCO input. Thus, VCO 40 will output a generated clock signal whose frequency is proportional to the filtered phase error signal. The VCO output signal is fed back through an optional frequency divider 50, which optionally divides the frequency by a number N. The frequency-divided clock signal is then input to the inverting input of the phase detector. For ease of illustration in FIGS. 1B, 1C,1D, it will be assumed that N=1 in divider 50, e.g., that the generated clock and the system clock have the same frequency. However, a common frequency for these two clock signals is not required for the present invention.
The quality of the generated clock signal is measured in terms of a system phase (or time) offset and jitter with respect to the system clock. For example, comparing FIGS. 1B and 1C, it is seen that some phase shift error (denoted as phase offset .phi.) will exist between the system clock signal and the generated clock signal. Ideally, there would be zero error, which would represent a perfect state of synchronization. Although the waveform of FIG. 1C is shown lagging the waveform of FIG. 1B by phase shift .phi., the FIG. 1C waveform might instead lead the waveform of FIG. 1B by a phase amount .phi..
In an actual PLL system, the magnitude of .phi. will vary with time, and the variation can go from lead-to-lag and vice versa as a function of time. Conventionally, The variation of .phi. with time (t) is commonly known as jitter, i.e., jitter=d.phi./dt. Of importance to the present invention is not so much d.phi./dt, but rather the maximum deviation of d.phi.. As used herein, jitter shall refer to the spread of maximum deviation in values of d.phi., without respect to time. Ideally, the magnitude of .phi. is small, e.g., very close to zero, and the amount of jitter (e.g., maximum deviation) would be very small if not zero. In FIG. 1D, the system clock, shown with bold lines, is superimposed upon the generated clock, in which jitter occurs on both sides of .phi.=0. Jitter could in fact exist solely on the positive or negative side of .phi.=0.
It is difficult to ensure that a generated clock signal will have small magnitude of .phi. and small, if not zero, jitter. It is therefore necessary to measure .phi. and the average d.phi. so that PLL clock generators that are out of specification can be rejected. In some instances, if the average maximum d.phi. is within an acceptable range and if .phi. is known, the effective magnitude of .phi. might be reduced by compensation.
Unfortunately, in practice it is difficult and time consuming to measure .phi. and especially to measure deviation in maximum average d.phi.. Typically measurements of phase shift are made over time using sophisticated and expensive analog laboratory equipment, whereupon .phi. and average maximum d.phi. may be approximated, subject to potentially substantial inaccuracies. Once these data are known, a measured PLL generator is either passed with respect to meeting .phi. and d.phi. specification, or is rejected and perhaps discarded. In some instances, measured PLL generators may be marked with the measured .phi. and d.phi. data for possible use in applications for which the measured amounts of phase and jitter are acceptable.
In summary, there is a need for a rapid and straightforward apparatus and method of testing PLL generators for phase and jitter. Preferably such testing should be capable of implementation on the integrated circuit containing the PLL generator. Further, such testing should be digital in nature, rapidly executing, and accurate in the reported results. In such an implementation, the PLL generator should optionally be able to compensate itself for excessive phase error, assuming that measured jitter is within an acceptable tolerance. On-IC generated measurement data for phase and/or jitter should be available to external digital equipment to permit marking the PLL generator for potential future, other, applications for which the observed phase and jitter may be acceptable.
The present invention provides such a method and apparatus.